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DATA DATA PRELIMINARY PRODUCTSHEET PRELIMINARY SHEET INFORMATION
PD70F3040, 70F3040Y
V850/SV1 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
TM
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD70F3040 and PD70F3040Y are products that substitute flash memory for the mask ROM of the
PD703039, 703040, 703041 and PD703039Y, 703040Y, 703041Y, respectively. Since the PD70F3040 and
70F3040Y can be read and written while mounted on the board, these products are ideal for evaluation during system development, multiple-version small-scale production or quick product release. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. V850/SV1 User's Manual Hardware: U14462E TM U10243E V850 Family User's Manual Architecture: FEATURES * Pin compatible with PD703039, 703040, 703041, 703039Y, 703040Y, and 703041Y * For mass production, these can be replaced by a mask ROM version.
PD70F3040
PD703039, 703040, 703041
PD70F3040Y PD703039Y, 703040Y, 703041Y
ORDERING INFORMATION
Part Number Package 176-pin plastic LQFP (fine-pitch) (24 x 24 mm) 176-pin plastic LQFP (fine-pitch) (24 x 24 mm)
PD70F3040GM-UEU PD70F3040YGM-UEU
DIFFERENCES BETWEEN V850/SV1 PRODUCTS
Internal ROM Internal RAM 16 KB IC None Provided 256 KB (mask ROM) 8 KB None Provided 16 KB None Provided 192 KB (mask ROM) 8 KB None Provided None
2
VPP Pin Provided
PD70F3040 PD70F3040Y PD703039 PD703039Y PD703040 PD703040Y PD703041 PD703041Y
256 KB (flash memory)
The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U14622EJ1V0DS00 (1st edition) Date Published March 2000 N CP(K) Printed in Japan
(c)
2000
PD70F3040, 70F3040Y
PIN CONFIGURATION
176-pin plastic LQFP (fine-pitch) (24 x 24 mm)
PD70F3040GM-UEU PD70F3040YGM-UEU
P12/SCK0/SCL0Note 2 P13/SI1/RXD0 P14/SO1/TXD0 P15/SCK1/ASCK0 P20/SI2/SDA1Note 2 P21/SO2 P22/SCK2/SCL1Note 2 P23/SI3/RXD1 P24/SO3/TXD1 P25/SCK3/ASCK1 P26/TI2/TO2 P27/TI3/TO3 VDD VSS P30/TI000 P31/TI001 P32/TI010 P33/TI011 P34/TO0 P35/TO1 P36/TI4/TO4 P37/TI5/TO5 P120/SI4 P121/SO4 P122/SCK4 P123/CLO P124/TI6/TO6 P125/TI7/TO7 P126/TI10/TO10 P127/TI11/TO11 P180 P181 P182 P183 P184 P185 P186 P187 VDD VSS P190 P191 P192 P193
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
P11/SO0 P10/SI0/SDA0Note 2 P113 P112 P111 P110 WAIT CLKOUT P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/AD15 P56/AD14 P55/AD13 P54/AD12 P53/AD11 P52/AD10 P51/AD9 P50/AD8 BVSS BVDD P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 P42/AD2 P41/AD1 P40/AD0 P96/HLDRQ P95/HLDAK P94/ASTB P93/DSTB/RD P92/R/W/WRH P91/UBEN P90/LBEN/WRL VSS VDD AVDD AVSS AVREF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
P87/ANI15 P86/ANI14 P85/ANI13 P84/ANI12 P83/ANI11 P82/ANI10 P81/ANI9 P80/ANI8 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 P147 P146 P145/RTPTRG1 P144/TI9/INTTI9 P143/INTCP93 P142/INTCP92 P141/INTCP91 P140/INTCP90 P137/TO81 P136/TO80 P135/TCLR8/INTTCLR8 P134/TI8/INTTI8 P133/INTCP83 P132/INTCP82 P131/INTCP81 P130/INTCP80 VSS VDD P07/INTP6 P06/INTP5/RTPTRG0 P05/INTP4/ADTRG P04/INTP3 P03/INTP2 P02/INTP1 P01/INTP0 P00/NMI P157/RTP17 P156/RTP16
Notes 1. Connect to VSS in normal operation mode. 2. SCL0, SCL1, SDA0, and SDA1 are valid only for the PD70F3040Y.
2
P194 P195 P196 P197 P170/KR0 P171/KR1 P172/KR2 P173/KR3 P174/KR4 P175/KR5 P176/KR6 P177/KR7 P160/PWM0 P161/PWM1 P162/PWM2 P163/PWM3 P164/CSYNCIN P165/VSOUT P166/HSOUT0 P167/HSOUT1 VPPNote 1 RESET XT1 XT2 VDD X2 X1 VSS P100/RTP00 P101/RTP01 P102/RTP02 P103/RTP03 P104/RTP04 P105/RTP05 P106/RTP06 P107/RTP07 VDD VSS P150/RTP10 P151/RTP11 P152/RTP12 P153/RTP13 P154/RTP14 P155/RTP15
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
PIN IDENTIFICATION
A16 to A21: AD0 to AD15: ADTRG: ANI0 to ANI15: ASCK0, ASCK1: ASTB: AVDD: AVREF: AVSS: BVDD: BVSS: CLKOUT: CLO: CSYNCIN: DSTB: HLDAK: HLDRQ: Address Bus Address/Data Bus AD Trigger Input Analog Input Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Bus Interface Power Supply Bus Interface Ground Clock Output Clock Output (divided) Csync Input Data Strobe Hold Acknowledge Hold Request P120 to P127: P130 to P137: P140 to P147: P150 to P157: P160 to P167: P170 to P177: P180 to P187: P190 to P197: PWM0 to PWM3: RD: RESET: RTP00 to RTP07,: RTP10 to RTP17 RTPTRG0, RTPTRG1: RTP Trigger Input R/W: RXD0, RXD1: SCK0 to SCK4: SCL0, SCL1: SDA0, SDA1: SI0 to SI4: SO0 to SO4: TCLR8: Key Return Lower Byte Enable Non-Maskable Interrupt Request Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 TI011, TI2 to TI11 TO0 to TO7, TO80,: TO81, TO10, TO11 TXD0, TXD1: UBEN: VDD: VPP: VSOUT: VSS: WAIT: WRH: WRL: X1, X2: XT1, XT2: Transmit Data Upper Byte Enable Power Supply Programming Power Supply Vsync Output Ground Wait Write Strobe High Level Data Write Strobe Low Level Data Crystal for Main System Clock Crystal for Subsystem Clock Timer Output Read/Write Status Receive Data Serial Clock Serial Clock Serial Data Serial Input Serial Output Timer Clear Port 12 Port 13 Port 14 Port 15 Port 16 Port 17 Port 18 Port 19 Pulse Width Modulation Read Reset Real-time Output Port
HSOUT0, HSOUT1: Hsync Output INTCP80 to INTCP83,: Interrupt Request from Peripherals INTCP90 to INTCP93, INTP0 to INTP6, INTTCLR8, INTTI8, INTTI9 KR0 to KR7: LBEN: NMI: P00 to P07: P10 to P15: P20 to P27: P30 to P37: P40 to P47: P50 to P57: P60 to P65: P70 to P77: P80 to P87: P90 to P96: P100 to P107: P110 to P113:
TI000, TI001, TI010,: Timer Input
Preliminary Data Sheet U14622EJ1V0DS00
3
PD70F3040, 70F3040Y
INTERNAL BLOCK DIAGRAM
NMI INTP0 to INTP6 INTCP80 to INTCP83, INTCP90 to INTCP93 INTTCLR8 INTTI8, INTTI9 TI000, TI001, TI010, TI011 TO0, TO1 TO80, TO81 TI8, TI9 TCLR8 TI2/TO2, TI3/TO3 TI4/TO4, TI5/TO5 TI6/TO6, TI7/TO7 TI10/TO10, TI11/TO11 CSYNCIN HSOUT0, HSOUT1, VSOUT SO0 SI0/SDA0Note 2 SCK0/SCL0Note 2 SO2 SI2/SDA1Note 2 SCK2/SCL1Note 2 SO1/TXD0 SI1/RXD0 SCK1/ASCK0 SO3/TXD1 SI3/RXD1 SCK3/ASCK1 SO4 SI4 SCK4 KR0 to KR7
INTC
ROM PC
CPU ROM correction Multiplier 16 x 16 32 BCU ALU
Instruction queue
HLDRQ HLDAK ASTB DSTB/RD R/W/WRH UBEN LBEN/WRL WAIT A16 to A21 AD0 to AD15
Note 1 Timer/counter 16-bit timers: TM0, TM1 8-bit timers: TM2 to TM7, TM10, TM11 24-bit timers: TM8, TM9
32-bit barrel shifter RAM System register General registers 32 bits x 32
16 KB
Vsync/Hsync SIO CSI0/I2C0Note 3 Ports CSI2/I2C1Note 3 CSI1/UART0 CSI3/UART1 Variable length CSI4 Key return function DMAC: 6 ch RTP
P190 to P197 P180 to P187 P170 to P177 P160 to P167 P150 to P157 P140 to P147 P130 to P137 P120 to P127 P110 to P113 P100 to P107 P90 to P96 P80 to P87 P70 to P77 P60 to P65 P50 to P57 P40 to P47 P30 to P37 P20 to P27 P10 to P15 P00 to P07
A/D converter CG
AVDD AVREF AVSS ANI0 to ANI15 ADTRG
CLKOUT CLO X1 X2 XT1 XT2 RESET
Watch timer Watchdog timer RTP00 to RTP07, RTP10 to RTP17 RTPTRG0, RTPTRG1
VDD VSS BVDD BVSS VPP
PWM0 to PWM3
PWM
Notes 1. 256 KB (Flash memory) 2. SDA0, SDA1, SCL0, and SCL1 are valid only for the PD70F3040Y.
2 3. The I C function is valid only for the PD70F3040Y.
4
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
CONTENTS
1.
PIN FUNCTIONS.................................................................................................................................. 6
1.1 1.2 1.3 Port Pins.................................................................................................................................................... 6 Non-Port Pins........................................................................................................................................... 10 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins ....................... 14
2. 3. 4.
ELECTRICAL SPECIFICATIONS...................................................................................................... 18 PACKAGE DRAWING ....................................................................................................................... 39 RECOMMENDED SOLDERING CONDITION.................................................................................. 40
Preliminary Data Sheet U14622EJ1V0DS00
5
PD70F3040, 70F3040Y
1. PIN FUNCTIONS 1.1 Port Pins
(1/4)
Pin Name P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 I/O No Port 4 8-bit I/O port Input/output mode can be specified in 1-bit units. I/O Yes Port 3 8-bit I/O port Input/output mode can be specified in 1-bit units. I/O Yes Port 2 8-bit I/O port Input/output mode can be specified in 1-bit units. I/O Yes Port 1 6-bit I/O port Input/output mode can be specified in 1-bit units. I/O I/O PULL Yes Function Port 0 8-bit I/O port Input/output mode can be specified in 1-bit units. Alternate Function NMI INTP0 INTP1 INTP2 INTP3 INTP4/ADTRG INTP5/RTPTRG0 INTP6 SI0/SDA0 SO0 SCK0/SCL0 SI1/RXD0 SO1/TXD0 SCK1/ASCK0 SI2/SDA1 SO2 SCK2/SCL1 SI3/RXD1 SO3/TXD1 SCK3/ASCK1 TI2/TO2 TI3/TO3 TI000 TI001 TI010 TI011 TO0 TO1 TI4/TO4 TI5/TO5 AD0 AD1 AD2 AD3 AD4
Remark
PULL: On-chip pull-up resistor
6
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
(2/4)
Pin Name P45 P46 P47 P50 P51 P52 P53 P54 P55 P56 P57 P60 P61 P62 P63 P64 P65 P70 P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 P84 P85 P86 P87 P90 P91 P92 P93 I/O No Port 9 7-bit I/O port Input/output mode can be specified in 1-bit units. Input No Port 8 8-bit input port Input No Port 7 8-bit input port I/O No Port 6 6-bit I/O port Input/output mode can be specified in 1-bit units. I/O No Port 5 8-bit I/O port Input/output mode can be specified in 1-bit units. I/O I/O PULL No Function Port 4 8-bit I/O port Input/output mode can be specified in 1-bit units. Alternate Function AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 A16 A17 A18 A19 A20 A21 ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 LBEN/WRL UBEN R/W/WRH DSTB/RD
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
7
PD70F3040, 70F3040Y
(3/4)
Pin Name P94 P95 P96 P100 P101 P102 P103 P104 P105 P106 P107 P110 P111 P112 P113 P120 P121 P122 P123 P124 P125 P126 P127 P130 P131 P132 P133 P134 P135 P136 P137 P140 P141 P142 P143 P144 P145 P146 P147 I/O No Port 14 8-bit I/O port Input/output mode can be specified in 1-bit units. I/O No Port 13 8-bit I/O port Input/output mode can be specified in 1-bit units. I/O No Port 12 8-bit I/O port Input/output mode can be specified in 1-bit units. SI4 SO4 SCK4 CLO TI6/TO6 TI7/TO7 TI10/TO10 TI11/TO11 INTCP80 INTCP81 INTCP82 INTCP83 TI8/INTTI8 TCLR8/INTTCLR8 TO80 TO81 INTCP90 INTCP91 INTCP92 INTCP93 TI9/INTTI9 RTPTRG1 - - I/O No Port 11 4-bit I/O port Input/output mode can be specified in 1-bit units. I/O Yes Port 10 8-bit I/O port Input/output mode can be specified in 1-bit units. I/O I/O PULL No Function Port 9 7-bit I/O port Input/output mode can be specified in 1-bit units. Alternate Function ASTB HLDAK HLDRQ RTP00 RTP01 RTP02 RTP03 RTP04 RTP05 RTP06 RTP07 - - - -
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
8
PD70F3040, 70F3040Y
(4/4)
Pin Name P150 P151 P152 P153 P154 P155 P156 P157 P160 P161 P162 P163 P164 P165 P166 P167 P170 P171 P172 P173 P174 P175 P176 P177 P180 P181 P182 P183 P184 P185 P186 P187 P190 P191 P192 P193 P194 P195 P196 P197 I/O No Port 19 8-bit I/O port Input/output mode can be specified in 1-bit units. I/O No Port 18 8-bit I/O port Input/output mode can be specified in 1-bit units. I/O Yes Port 17 8-bit I/O port Input/output mode can be specified in 1-bit units. I/O No Port 16 8-bit I/O port Input/output mode can be specified in 1-bit units. I/O I/O PULL No Function Port 15 8-bit I/O port Input/output mode can be specified in 1-bit units. Alternate Function RTP10 RTP11 RTP12 RTP13 RTP14 RTP15 RTP16 RTP17 PWM0 PWM1 PWM2 PWM3 CSYNCIN VSOUT HSOUT0 HSOUT1 KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 - - - - - - - - - - - - - - - -
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
9
PD70F3040, 70F3040Y
1.2 Non-Port Pins
(1/4)
Pin Name A16 to A21 AD0 to AD7 AD8 to AD15 ADTRG ANI0 to ANI7 ANI8 to ANI15 ASCK0 ASCK1 ASTB AVDD Output - No - External address strobe signal output Positive power supply for A/D converter and ports used for alternate functions Reference voltage input for A/D converter Ground potential for A/D converter and ports used for alternate functions Positive power supply for bus interface and ports used for alternate functions Ground potential for bus interface and ports used for alternate functions Internal system clock output CLO output signal Csync signal input External data strobe signal output Bus hold acknowledge output Bus hold request input Hsync signal output before compensation Hsync signal output after compensation Input No External capture input for CC80 to CC83 P123 P164 P93/RD P95 P96 P166 P167 P130 to P133 Input Input Input Input Yes No No Yes Baud rate clock input for UART0 and UART1 A/D converter external trigger input Analog input to A/D converter I/O Output I/O PULL No No Address bus 16 to 21 Address/data multiplexed bus 0 to 15 Function Alternate Function P60 to P65 P40 to P47 P50 to P57 P05/INTP4 P70 to P77 P80 to P87 P15/SCK1 P25/SCK3 P94 -
AVREF AVSS
Input -
- -
- -
BVDD
-
-
-
BVSS
-
-
-
CLKOUT CLO CSYNCIN DSTB HLDAK HLDRQ HSOUT0 HSOUT1 INTCP80 to INTCP83 INTCP90 to INTCP93 INTP0 to INTP3 INTP4 INTP5 INTP6
Output Output Input Output Output Input Output
- No No No No No No
-
Input
No
External capture input for CP90 to CP93
P140 to P143
Input
Yes
External interrupt request input (analog noise elimination) External interrupt request input (digital noise elimination)
P01 to P04 P05/ADTRG P06/RTPTRG0
External interrupt request input (digital noise elimination supporting remote controller)
P07
Remark
PULL: On-chip pull-up resistor
10
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
(2/4)
Pin Name INTTCLR8 INTTI8 INTTI9 KR0 to KR7 LBEN NMI PWM0 to PWM3 RD RESET RTP00 to RTP07 RTP10 to RTP17 RTPTRG0 RTPTRG1 R/W RXD0 RXD1 SCK0 SCK1 SCK2 SCK3 SCK4 SCL0 SCL1 SDA0 SDA1 SI0 SI1 SI2 SI3 SI4 SO0 SO1 SO2 SO3 SO4 TCLR8 Input No No Variable-length CSI4 serial transmit data output External clear input for TM8 Output No Yes Variable-length CSI4 serial receive data input (3-wire mode) Serial transmit data output for CSI0 to CSI3 Input Yes I/O Yes I/O No Yes Variable-length CSI4 serial clock I/O Serial clock I/O for I C0 and I C1 (PD70F3040Y) Serial transmit/receive data I/O for I C0 and I C1 (PD70F3040Y) Serial receive data input for CSI0 to CSI3 (3-wire mode)
2 2 2 2
I/O Input Input
PULL No No
Function External interrupt request input (digital noise elimination)
Alternate Function P135/TCLR8 P134/TI8 P144/TI9
Input Output Input Output Output Input Output
Yes No Yes No No - Yes
Key return input Lower byte enable signal output for external data bus Non-maskable interrupt request input Output of PWM channels 0 to 3 Bus read strobe signal output System reset input Real-time output port
P170 to P177 P90/WRL P00 P160 to P163 P93/DSTB - P100 to P107 P150 to P157
Input
Yes No
RTP external trigger input
P06 P146
Output Input
No Yes
External read/write status output Serial receive data input for UART0 and UART1
P92/WRH P13/SI1 P23/SI3
I/O
Yes
Serial clock I/O for CSI0 to CSI3 (3-wire mode)
P12/SCL0 P15/ASCK0 P22/SCL1 P25/ASCK1 P122 P12/SCK0 P22/SCK2 P10/SI0 P20/SI2 P10/SDA0 P13/RXD0 P20/SDA1 P23/RXD1 P120 P11 P14/TXD0 P21 P24/TXD1 P121 P135/INTTCLR8
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
11
PD70F3040, 70F3040Y
(3/4)
Pin Name TI000 TI001 TI010 TI011 TI2 TI3 TI4 TI5 TI6 TI7 TI8 TI9 TI10 TI11 TO0 TO1 TO2 TO3 TO4 TO5 TO6 TO7 TO80 TO81 TO10 TO11 TXD0 TXD1 UBEN VDD VPP VSOUT VSS WAIT WRH WRL Output - - Output - Input Output No - - No - No No Higher byte enable signal output for external data bus Positive power supply pin High voltage application pin for program write/verify Vsync signal output Ground potential External WAIT signal input Higher byte write strobe signal output for external data bus Lower byte write strobe signal output for external data bus P92/R/W P90/LBEN P165 - - Output Yes No Output Yes No I/O Input PULL Yes Function External count clock input/external capture trigger input for TM0 External capture trigger input for TM0 External count clock input/external capture trigger input for TM1 External capture trigger input for TM1 External count clock input for TM2 External count clock input for TM3 External count clock input for TM4 External count clock input for TM5 External count clock input for TM6 External count clock input for TM7 External count clock input for TM8 External count clock input for TM9 External count clock input for TM10 External count clock input for TM11 Pulse signal output for TM0 Pulse signal output for TM1 Pulse signal output for TM2 Pulse signal output for TM3 Pulse signal output for TM4 Pulse signal output for TM5 Pulse signal output for TM6 Pulse signal output for TM7 Pulse signal output 0 for TM8 Pulse signal output 1 for TM8 Pulse signal output for TM10 Pulse signal output for TM11 Serial transmit data output for UART0 and UART1 Alternate Function P30 P31 P32 P33 P26/TO2 P27/TO3 P36/TO4/A15 P37/TO5 P124/TO6 P125/TO7 P134/INTTI8 P144/INTTI9 P126/TO10 P127/TO11 P34 P35 P26/TI2 P27/TI3 P36/TI4 P37/TI5 P124/TI6 P125/TI7 P136 P137 P126/TI10 P127/TI11 P14/SO1 P24/SO3 P91 - -
Remark
PULL: On-chip pull-up resistor
12
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
(4/4)
Pin Name X1 X2 XT1 XT2 I/O Input - Input - No Resonator connection for subsystem clock PULL No Function Resonator connection for main system clock Alternate Function - - - -
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
13
PD70F3040, 70F3040Y
1.3 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins
Table 1-1 shows the input/output circuit type of each pin and the recommended connection of unused pins. For the input/output configuration of each type, refer to Figure 1-1. Table 1-1. Types of Pin I/O Circuit and Recommended Connection of Unused Pins (1/2)
Pin Alternate Function I/O Circuit Type 5-W I/O Buffer Power Supply VDD Input: Output: Recommended Connection Method
P00 P01 to P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P20 P21 P22 P23 P24 P25 P26, P27 P30, P31 P32, P33 P34, P35 P36 P37 P40 to P47 P50 to P57 P60 to P65 P70 to P77 P80 to P87 P90 P91 P92 P93 P94 P95 P96 P100 to P107 P110 to P113 P120
NMI INTP0 to INTP3 INTP4/ADTRG INTP5/RTPTRG0 INTP6 SI0/SDA0 SO0 SCK0/SCL0 SI1/RXD0 SO1/TXD0 SCK1/ASCK0 SI2/SDA1 SO2 SCK2/SCL1 SI3/RXD1 SO3/TXD1 SCK3/ASCK1 TI2/TO2, TI3/TO3 TI000, TI001 TI010, TI011 TO0, TO1 TI4/TO4 TI5/TO5 AD0 to AD7 AD8 to AD15 A16 to A21 ANI0 to ANI7 ANI8 to ANI15 LBEN/WRL UBEN R/W/WRH DSTB/RD ASTB HLDAK HLDRQ RTP00 to RTP07 - SI4
Independently connect to VDD or VSS via a resistor Leave open
10-F 10-E 10-F 5-W 10-E 10-F 10-F 10-E 10-F 5-W 10-E 10-F 5-W 5-W
VDD
VDD
VDD
5-A 5-W
5 5 5 9 9 5
BVDD BVDD BVDD AVDD AVDD BVDD
Input: Output:
Independently connect to BVDD or BVSS via a resistor Leave open
Connect to AVSS
Input: Output:
Independently connect to BVDD or BVSS via a resistor Leave open
10-E 5 5-K
VDD VDD VDD
Input: Output:
Independently connect to VDD or VSS via a resistor Leave open
14
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
Table 1-1. Types of Pin I/O Circuit and Recommended Connection of Unused Pins (2/2)
Pin Alternate Function I/O Circuit Type 10-G 10-H 5 5-K Output: I/O Buffer Power Supply VDD Input: Recommended Connection Method
P121 P122 P123 P124 P125 P126 P127 P130 to P133 P134 P135 P136, P137 P140 to P143 P144 P145 P146, P147 P150 to P157 P160 to P163 P164 P165 P166 P167 P170 to P177 P180 to P187 P190 to P197 CLKOUT WAIT RESET X1 X2 XT1 XT2 AVREF VPP VDD VSS AVDD AVSS BVDD BVSS
SO4 SCK4 CLO TI6/TO6 TI7/TO7 TI10/TO10 TI11/TO11 INTCP80 to INTCP83 TI8/INTTI8 TCLR8/INTTCLR8 TO80, TO81 INTCP90 to INTCP93 TI9/INTTI9 RTPTRG1 - RTP10 to RTP17 PWM0 to PWM3 CSYNCIN VSOUT HSOUT0 HSOUT1 KR0 to KR7 - - - - - - - - - - - - - - - - -
Independently connect to VDD or VSS via a resistor Leave open
5-K
VDD
5 5-K VDD
5 5 5 5-K 5 VDD VDD
5-K 5 5 4 1 2 - - - - - - - - - - - -
VDD VDD VDD BVDD BVDD VDD VDD VDD VDD VDD - - - - - - - - Connect to VDD Connect to VSS Connect to VDD Connect to VSS Leave open Connect to VSS Leave open Connect to AVSS Connect to VSS - - Leave open Connect to VDD via a resistor - -
Preliminary Data Sheet U14622EJ1V0DS00
15
PD70F3040, 70F3040Y
Figure 1-1. Pin Input/Output Circuits (1/2)
Type 1
Type 5 VDD VDD P-ch IN N-ch Output disable N-ch Data P-ch IN/OUT
Input enable
Type 2
Type 5-A
VDD
Pullup enable Data IN Output disable Input enable Type 5-K VDD Data Data P-ch OUT Output disable N-ch Output disable
P-ch VDD P-ch IN/OUT N-ch
Schmitt-triggered input with hysteresis characteristics Type 4
VDD P-ch IN/OUT N-ch
Push-pull output that can be set for high impedance output (both P-ch and N-ch are off)
Input enable
16
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
Figure 1-1. Pin Input/Output Circuits (2/2)
Type 5-W
VDD
Type 10-F
VDD
Pullup enable Data
P-ch VDD P-ch IN/OUT
Pullup enable Data
P-ch VDD P-ch IN/OUT
Output disable Input enable Type 9
N-ch
Open Output disable Input enable Type 10-G
N-ch
VDD P-ch IN N-ch
+ -
Data Comparator
P-ch IN/OUT
Open drain VREF (Threshold voltage) Output disable N-ch
Input enable
Input enable
Type 10-E
VDD
Type 10-H VDD
Pullup enable Data
P-ch VDD
Data
P-ch IN/OUT
P-ch IN/OUT
Open Output disable Input enable
Open drain Output disable
N-ch
N-ch Input enable
Preliminary Data Sheet U14622EJ1V0DS00
17
PD70F3040, 70F3040Y
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C, VSS = 0 V)
Parameter Supply voltage Symbol VDD AVDD BVDD AVSS BVSS Input voltage VI1 VI2 VI3 Clock input voltage Analog input voltage Analog reference input voltage Output current, low VK VIAN AVREF IOL Note 1 (VDD) Note 2 (BVDD) VPP X1, XT1, VDD = 2.7 to 3.6 V Note 3 (AVDD) AVREF pin Per pin Total for P00 to P07 and P150 to P157 Total for P100 to P107 and P160 to P167 Total for P170 to P177 and P190 to P197 Total for P124 to P127 and P180 to P187 Total for P30 to P37 and P120 to P123 Total for P12 to P15, P20 to 27, and P110 to P113 Total for P50 to P57, P60 to P65, and CLKOUT Total for P40 to P47 and P90 to P96 Total for P130 to P137 and P140 to P147 Output current, high IOH Per pin Total for P00 to P07 and P150 to P157 Total for P100 to P107 and P160 to P167 Total for P170 to P177 and P190 to P197 Total for P124 to P127 and P180 to P187 Total for P30 to P37 and P120 to P123 Total for P12 to P15, P20 to 27, and P110 to P113 Total for P50 to P57, P60 to P65, and CLKOUT Total for P40 to P47 and P90 to P96 Total for P130 to P137 and P140 to P147 Output voltage VO1 VO2 Operating ambient temperature TA Note 1 (VDD) Note 2 (BVDD) Normal operation mode Flash programming mode Storage temperature Tstg Conditions Ratings -0.5 to +4.6 -0.5 to +4.6 -0.5 to +4.6 -0.5 to +0.5 -0.5 to +0.5 -0.5 to VDD + 0.5
Note 4 Note 4
Unit V V V V V V V V
Note 4
-0.5 to BVDD + 0.5 -0.5 to +8.5 -0.5 to VDD + 1.0
V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
-0.5 to AVDD + 0.5 -0.5 to AVDD + 0.5 4.0 25 25 25 25 25 25 25 25 25 -4.0 -25 -25 -25 -25 -25 -25 -25 -25 -25 -0.5 to VDD + 0.5
Note 4
Note 4
Note 4
V V C C C
-0.5 to BVDD + 0.5 -40 to +85 +10 to +40 -40 to +125
Note 4
Notes 1. Ports 0, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, RESET (including alternate-function pins) 2. Ports 4, 5, 6, 9, WAIT (including alternate-function pins) 3. Ports 7, 8 (including alternate-function pins) 4. Be sure not to exceed each absolute maximum rating (MAX.).
18
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or VCC and GND. However, direct connections among open-drain and open-connector pins are possible, as are direct connections to external circuits that have timing designed to prevent output contention with pins that become high-impedance. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation.
Capacitance (TA = 25C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance Output capacitance Symbol CI CIO CO Conditions fC = 1 MHz Unmeasured pins returned to 0 V MIN. TYP. MAX. 15 15 15 Unit pF pF pF
Operating Conditions
(1) CPU Operation Frequency
Parameter CPU operation frequency Symbol fCPU Conditions When main system clock is operating When subsystem clock is operating MIN. 0.5 32.768 TYP. MAX. 16 Unit MHz kHz
(2) Supply Voltage
Parameter Supply voltage Symbol VDD AVDD BVDD Conditions MIN. 2.7 2.7 2.7 TYP. MAX. 3.6 3.6 3.6 Unit V V V
(3) Operating Frequency for Each Supply Voltage
Internal Operating Clock Frequency 4 MHz fXX 16 MHz fXT = 32.768 kHz Supply Voltage (VDD = AVDD = BVDD) 2.7 to 3.6 V 2.7 to 3.6 V
Preliminary Data Sheet U14622EJ1V0DS00
19
PD70F3040, 70F3040Y
Recommended Oscillator
(1) Main System Clock Oscillator (TA = -40 to +85C)
X2
X1
Parameter Oscillation frequency Oscillation stabilization time
Symbol fXX
Conditions
MIN. 4
TYP.
MAX. 16
Unit MHz s s
After reset release After STOP mode release
2 /fXX Note
19
Note Values vary depending on the settings of the oscillation stabilization selection register (OSTS). Remarks 1. Place the oscillator as close as possible to X1 and X2. 2. Do not wire other signal lines within the broken lines. 3. For resonator selection and oscillation constants, customers are advised to either evaluate the oscillation themselves, or apply to the resonator manufacturer for evaluation.
20
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
(2) Subsystem Clock Oscillator (TA = -40 to +85C)
XT1
XT2
Parameter Oscillation frequency Oscillation stabilization time
Symbol fXT
Conditions
MIN. 32
TYP. 32.768 10
MAX. 35
Unit kHz s
Remarks 1. Place the oscillator as close as possible to XT1 and XT2. 2. Do not wire other signal lines within the broken lines. 3. For resonator selection and oscillation constants, customers are advised to either evaluate the oscillation themselves, or apply to the resonator manufacturer for evaluation.
Preliminary Data Sheet U14622EJ1V0DS00
21
PD70F3040, 70F3040Y
DC Characteristics (TA = -40 to +85C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 VIH4 VIH5 Input voltage, low VIL1 VIL2 VIL3 VIL4 VIL5 Output voltage, high VOH1 VOH2 Output voltage, low VOL1 VOL2 Conditions Pins in Note 1, WAIT Pins in Note 2 Pins in Note 3, RESET Pins in Note 4 X1, XT1, XT2 Pins in Note 1, WAIT Pins in Note 2 Pins in Note 3, RESET Pins in Note 4 X1, XT1, XT2 Note 1, CLKOUT Notes 2, 3 Note 1, CLKOUT Notes 2, 3 (excluding P10, 12, 20, 22) VOL3 Input leakage current, high ILIH1 P10, 12, 20, 22 VI = VDD = AVDD = BVDD Other than X1, XT1, XT2 X1, XT1, XT2 VI = 0 V Other than X1, XT1, XT2 X1, XT1, XT2 VO = VDD = AVDD = BVDD VO = 0 V Normal operation (fXX = 16 MHz) HALT mode (fXX = 16 MHz) IDLE mode (fXX = 16 MHz) STOP mode (subsystem clock operation: fXT = 32.768 kHz, watch timer operation STOP mode (subsystem clock stopped) Pull-up resistor RL 10 45 20 6 13 0.4 5 V IOH = -3 mA IOH = -1 mA MIN. 0.7BVDD 0.7VDD 0.75VDD 0.7AVDD 0.8VDD BVSS - 0.5 VSS - 0.5 VSS - 0.5 AVSS - 0.5 VSS 0.8BVDD 0.8VDD 0.4 0.4 TYP. MAX. BVDD VDD VDD AVDD VDD 0.3BVDD 0.3VDD 0.3VDD 0.3AVDD 0.2VDD Unit V V V V V V V V V V V V V V
A A A A A A
mA mA mA
ILIH2 Input leakage current, low ILIL1
20 -5
ILIL2 Output leakage current, high Output leakage current, low Supply current ILOH ILOL IDD1 IDD2 IDD3 IDD4
-20 5 -5 65 35 14 115
A
1 30
100 100
A
k
Notes 1. Ports 4, 5, 6, 9 (including alternate-function pins) 2. P11, P14, P21, P24, P34, P35, P100 to P107, P110 to P113, P121, P123, P136, P137, P146, P147, P150 to P157, P160 to P163, P165 to P167, P180 to P187, P190 to P197 (including alternate-function pins) 3. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, P120, P122, P124 to P127, P130 to P135, P140 to P145, P164, P170 to P177 (including alternate-function pins) 4. Ports 7, 8 (including alternate-function pins) Caution The TYP. value of VDD is 3.3 V. The current that is consumed at output buffers is not included.
22
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
Data Retention Characteristics (TA = -40 to +85C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V )
Parameter Data retention voltage Data retention current Supply voltage rise time Supply voltage fall time Supply voltage hold time (from STOP mode setting) STOP release signal input time Data retention high-level input voltage Data retention low-level input voltage Symbol VDDDR IDDDR tRVD tFVD tHVD Conditions STOP mode VDDDR [V] 200 200 0 MIN. 1.8 1 TYP. MAX. 3.6 100 Unit V
A s s
ms
tDREL VIHDR VILDR All input ports All input ports
0 VIHn 0 VDDDR VILn
ms V V
Remark n = 1 to 5
Setting STOP mode
tFVD
tRVD
VDD tHVD VDDDR tDREL
RESET (input)
VIHDR
NMI, INTP0 to INTP3 (input)
VIHDR
STOP release interrupt (NMI) (when STOP mode is released at rising edge)
VILDR
Caution Be sure to shift to and return from STOP mode when VDD is 2.7 V or higher.
Preliminary Data Sheet U14622EJ1V0DS00
23
PD70F3040, 70F3040Y
AC Characteristics AC Test Input Waveforms (VDD, BVDD, AVDD)
VDD
VIH Test points VIL
VIH VIL
0V
AC Test Output Test Point (BVDD)
VOH Test points VOL
VOH VOL
Load Conditions
DUT (Device under test) CL = 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
24
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
Clock Timing Operating Condition (TA = -40 to +85C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter X1 input cycle XT1 input cycle X1 input high-level width XT1 input high-level width X1 input low-level width XT1 input low-level width X1 input rise time X1 input fall time CLKOUT output cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time tXR tXF tCYK tWKH tWKL tKR tKF <4> <5> <6> <7> <8> <9> <10> 62.5 ns 0.4 (T-20) 0.4 (T-20) 10 10 tWXL <3> tWXH <2> Symbol tCYX <1> Conditions MIN. 62.5 28.6 31.2 14.3 31.2 14.3 MAX. 250 31.2 125 15.6 125 15.6
(< 1 > - < 2 > - < 3 > )/2 (< 1 > - < 2 > - < 3 > )/2
Unit ns
s
ns
s
ns
s
ns ns
31.2 s ns ns ns ns
Remark T = tCYK Clock Timing
<1> <2> <3>
X1, XT1 (input)
<4>
<5> <7>
<6> <8>
CLKOUT (output)
<9>
<10>
Timing of Pins Other Than X1 and CLKOUT Pins (TA = -40 to +85C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, Output Pin Load Capacitance: CL = 50 pF)
Parameter Output rise time Output fall time Symbol tOR tOF Conditions MIN. MAX. 20 20 Unit ns ns
Preliminary Data Sheet U14622EJ1V0DS00
25
PD70F3040, 70F3040Y
Bus Timing (CLKOUT Asynchronous) (TA = -40 to +85C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter Address setup time (to ASTB) Address hold time (from ASTB) Address float from DSTB Setup time from address to data input Setup time from DSTB to data input Delay time from ASTB to DSTB Data input hold time (from DSTB) Address output time from DSTB Delay time from DSTB to ASTB Delay time from DSTB to ASTB DSTB low-level width ASTB high-level width Data output time from DSTB Data output setup time (to DSTB) Data output hold time (from DSTB) WAIT setup time (to address) Symbol tSAST tHSTA tFDA tDAID tDDID tDSTD tHDID tDDA tDDST1 tDDST2 tWDL tWSTH tDDOD tSODD tHDOD tSAWT1 tSAWT2 WAIT hold time (from address) tHAWT1 tHAWT2 WAIT setup time (to ASTB) tSSTWT1 tSSTWT2 WAIT hold time (from ASTB) tHSTWT1 tHSTWT2 HLDRQ high-level width HLDAK low-level width Delay time from HLDAK to bus output Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK tWHQH tWHAL tDHAC tDHQHA1 tDHQHA2 <11> <12> <13> <14> <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> <27> <28> <29> <30> <31> <32> <33> <34> <35> <36> <37> <38> n1 nT + 5 (1 + n)T + 5 T + 10 T - 15 0 1.5T 0.5T (2n + 7.5)T + 25 1.5T + 25 n1 n1 (0.5 + n)T (1.5 + n)T 1.5T - 25 (1 + n)T - 5 n1 (1 + n)T - 20 T - 15 1.5T - 30 (1.5 + n)T - 30 0.5T - 15 0 (1 + i)T - 15 0.5T - 15 (1.5 + i)T - 15 (1 + n)T - 15 T - 15 15 Conditions MIN. 0.5T - 20 0.5T - 15 2 (2 + n)T - 30 (1 + n)T - 30 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = 1/fCPU (fCPU: CPU operation clock frequency) 2. n: Number of wait clocks inserted in the bus cycle. Sampling timing changes when a programmable wait is inserted. 3. i: Number of idle states inserted after the read cycle (0 or 1). 4. The specifications described above are the values of when a clock with a duty ratio of 1:1 is input from X1.
26
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
Bus Timing (CLKOUT Synchronous) (TA = -40 to +85C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to DSTB Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Delay time from CLKOUT to data output WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to address float Delay time from CLKOUT to HLDAK Symbol tDKA tFKA <39> <40> Conditions MIN. 0 -12 MAX. 19 7 Unit ns ns
tDKST tDKD tSIDK tHKID tDKOD
<41> <42> <43> <44> <45>
-12 -5 15 5
7 14
ns ns ns ns
19
ns
tSWTK tHKWT tSHQK tHKHQ tDKF
<46> <47> <48> <49> <50>
15 5 15 5 19
ns ns ns ns ns
tDKHA
<51>
19
ns
Remark The specifications described above are the values of when a clock with a duty ratio of 1:1 is input from X1.
Preliminary Data Sheet U14622EJ1V0DS00
27
PD70F3040, 70F3040Y
Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
T1
T2
TW
T3
CLKOUT (output) <39> A16 to A21 (output), Note <14> <43> <40> AD0 to AD15 (I/O) Address <41> <12> <11> ASTB (output) <22> <42> <16> <13> <15> <42> <19> <18> <20> <21> <46> Hi-Z Data <41> <17> <44>
DSTB (output), RD (output) <30> <46> <32> <31> <33> <47> <47>
WAIT (input) <26> <28> <27> <29>
Note R/W (output), UBEN (output), LBEN (output) Remark WRL and WRH are high level.
28
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
T1
T2
TW
T3
CLKOUT (output) <39> A16 to A21 (output), Note <45> AD0 to AD15 (I/O) Address <41> <12> <11> Data <41>
ASTB (output) <22> <42> <16> DSTB (output), WRL (output), WRH (output) <30> <46> <32> <31> <33> <47> <21> <46> <47> <23> <42> <24> <25> <19>
WAIT (input) <26> <28> <27> <29>
Note R/W (output), UBEN (output), LBEN (output) Remark RD is high level.
Preliminary Data Sheet U14622EJ1V0DS00
29
PD70F3040, 70F3040Y
Bus Hold
TH CLKOUT (output) <48> <49>
TH
TH
TI
<48> <34>
HLDRQ (input)
<51> <37> <38>
<51>
HLDAK (output) <50> <35> A16 to A21 (output), Note Hi-Z <36>
AD0 to AD15 (I/O)
Data
Hi-Z
ASTB (output)
Hi-Z
DSTB (output), RD (output), WRL (output), WRH (output)
Hi-Z
Note R/W (output), UBEN (output), LBEN (output)
30
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
Reset/Interrupt Timing (TA = -40 to +85C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter RESET high-level width RESET low-level width NMI high-level width NMI low-level width INTPn high-level width Symbol tWRSH tWRSL tWNIH tWNIL tWITH <52> <53> <54> <55> <56> n = 0 to 3, analog noise elimination n = 4, 5, digital noise elimination n = 6, digital noise elimination INTPn low-level width tWITL <57> n = 0 to 3, analog noise elimination n = 4, 5, digital noise elimination n = 6, digital noise elimination Conditions MIN. 500 500 500 500 500 3T + 20 3Tsmp + 20 500 3T + 20 3Tsmp + 20 MAX. Unit ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = 1/fXX 2. Tsmp = Noise elimination sampling clock frequency Reset
<52>
<53>
RESET (input)
Interrupt
<54>
<55>
NMI (input)
<56>
<57>
INTPn (input)
Remark n = 0 to 6
Preliminary Data Sheet U14622EJ1V0DS00
31
PD70F3040, 70F3040Y
TIn Input Timing (TA = -40 to +85C, VDD = AVDD =BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter Tln0, Tln1 (n = 00, 01) High-level width Tln (n = 2 to 7, 10, 11) High-level width Tln0, Tln1 (n = 00, 01) Low-level width Tln (n = 2 to 7, 10, 11) Low-level width 3/fXX + 20 ns tTIL <59> 2Tsam + 20
Note
Symbol tTIIH <58>
Conditions
MIN. 2Tsam + 20
Note
MAX.
Unit ns
3/fXX + 20
ns
ns
Note Tsam can be selected by setting the PRMn1 and PRMn0 bits of prescaler mode registers n0, n1 (PRMn0, PRMn1) (n = 0, 1). TM0 (PRM00, PRM01 registers): Tsam = 2/fXX, 4/fXX, 16/fXX, 64/fXX, 256/fXX, 1/INTWTI period TM1 (PRM10, PRM11 registers): Tsam = 2/fXX, 4/fXX, 16/fXX, 32/fXX, 128/fXX, 256/fXX However, when the TIn0 valid edge is selected as the count clock, Tsam = 4/fXX (n = 0, 1).
<58>
<59>
TIn
Remark n = 000, 001, 010, 011, 10, 11, 2 to 7
32
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
3-Wire SIO Timing (1) Master Mode (TA = -40 to +85C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter SCKn cycle time SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) Delay time from SCKn to SOn output Symbol tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1 <60> <61> <62> <63> <64> <65> Conditions MIN. 400 140 140 50 50 60 MAX. Unit ns ns ns ns ns ns
Remark n = 0 to 3 (2) Slave Mode (TA = -40 to +85C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter SCKn cycle time SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) Delay time from SCKn to SOn output Symbol tKCY2 tKH2 tKL2 tSIK2 tKSI2 tKSO2 <60> <61> <62> <63> <64> <65> Conditions MIN. 400 140 140 50 50 60 MAX. Unit ns ns ns ns ns ns
Remark n = 0 to 3
<60> <61> <62> <63> SIn (input) <65> SOn (output) <64>
SCKn (I/O)
Remark n = 0 to 3
Preliminary Data Sheet U14622EJ1V0DS00
33
PD70F3040, 70F3040Y
3-Wire Variable-Length CSI Timing (1) Master Mode (TA = -40 to +85C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter SCK4 cycle time SCK4 high-level width SCK4 low-level width SI4 setup time (to SCK4) SI4 hold time (from SCK4) Delay time from SCK4 to SO4 output Symbol tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1 <66> <67> <68> <69> <70> <71> Conditions MIN. 400 140 140 50 50 60 MAX. Unit ns ns ns ns ns ns
(2) Slave Mode (TA = -40 to +85C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter SCK4 cycle time SCK4 high-level width SCK4 low-level width SI4 setup time (to SCK4) SI4 hold time (from SCK4) Delay time from SCK4 to SO4 output Symbol tKCY2 tKH2 tKL2 tSIK2 tKSI2 tKSO2 <66> <67> <68> <69> <70> <71> Conditions MIN. 400 140 140 50 50 60 MAX. Unit ns ns ns ns ns ns
<66> <67> <68> <69> SI4 (input) <71> SO4 (output) <70>
SCK4 (I/O)
34
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
UART Timing (TA = -40 to +85C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter ASCKn cycle time ASCKn high-level width ASCKn low-level width Symbol tKCY13 tKH13 tKL13 <72> <73> <74> Conditions MIN. 200 80 80 MAX. Unit ns ns ns
Remark n = 0, 1
<72> <73> <74>
ASCKn (input)
Remark n = 0, 1
Preliminary Data Sheet U14622EJ1V0DS00
35
PD70F3040, 70F3040Y
I C Bus Mode (Only for PD70F3040Y)
2
(TA = -40 to +85C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)
Parameter Symbol Standard Mode MIN. SCLn clock frequency Bus free time (between stop/start conditions) Hold time
Note 1
High-Speed Mode MIN. 0 1.3 MAX. 400 -
Unit
MAX. 100 -
fCLK tBUF <75>
0 4.7
kHz
s s s s s s s
ns ns ns
tHD : STA tLOW tHIGH tSU : STA
<76> <77> <78> <79> <80>
4.0 4.7 4.0 4.7 5.0 0
Note 2
- - - - - - - 1000 300 - -
0.6 1.3 0.6 0.6 - 0
Note 2
- - - - - 0.9
Note 3
SCLn clock low-level width SCLn clock high-level width Setup time of start/restart conditions Data hold time Data setup time Rising time of SDAn and SCLn signals Falling time of SDAn and SCLn signals Setup time of stop condition Pulse width of spike suppressed by input filter Load capacitance of bus line
CBUS-compatible master tHD : DAT I C mode tSU : DAT tR tF tSU : STO tSP
2
<81> <82> <83> <84> <85>
250 - - 4.0 -
100
Note 4
-
Note 5
20 + 0.1Cb 20 + 0.1Cb 0.6 0
300 300 - 50
Note 5
s
ns
Cb
-
400
-
400
pF
Notes 1. The first clock pulse in the start condition is generated after the hold time. 2. The system must internally provide at least 300-ns hold time for the SDAn signal (at VIHmin. of the SCLn signal) in order to fill the undefined period that appears at the SCLn falling edge. 3. If the system does not extend the low hold time (tLOW), it is required to satisfy only the maximum data hold time (tHD: DAT).
2 2 4. The high-speed I C bus is available in the standard mode I C bus system. In this case, following
conditions should be satisfied. * When the system does not extend the low-state hold time of the SCLn signal tSU: DAT 250 ns * When the system extends the low-state hold time of the SCLn signal Before the SCLn line is released (tRmax. + tSU: 5. Cb: Total capacitance of one bus line (Unit: pF) Remark n = 0, 1
DAT
= 1000 + 250 = 1250 ns: Standard mode I2C bus
specification), send the next data bit to the SDAn line.
36
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
I C Bus Mode (PD70F3040Y only)
2
<77> SCLn
<82>
<80> <76>
<78>
<83> <79> <81> <76> <85> <84>
SDAn <75> Stop Strat condition condition Restart condition Stop condition
Remark
n = 0, 1
A/D Converter (TA = -40 to +85C, VDD = AVDD = AVREF = 2.7 to 3.6 V, AVSS = VSS = 0 V, Output Pin Load Capacitance: CL = 50 pF)
Parameter Resolution Overall error
Note 1
Symbol
Conditions
MIN. 10
TYP. 10
MAX. 10 0.8
Unit bit %FSR
Conversion time Zero-scale error Full-scale error
Note 1
tCONV
5
100 0.4 0.4
s
%FSR %FSR LSB LSB V V
Note 1
Integral linearity error
Note 2
4.0 4.0 AVREF VIAN AIREF AIDD AVREF = AVDD 2.7 AVSS 240 1 3.6 AVREF 360 3
Differential linearity error
Note 2
Analog reference voltage Analog input voltage AVREF current Supply current
A
mA
Notes 1. Excluding quantization error (0.05%FSR) 2. Excluding quantization error (0.5LSB) Remark LSB: Least Significant Bit FSR: Full Scale Range
Preliminary Data Sheet U14622EJ1V0DS00
37
PD70F3040, 70F3040Y
Flash Memory Programming Mode Write/Erase Characteristics (TA = 10 to 40C, VDD = 3.0 to 3.6 V)
Parameter Write current Symbol IDDW IPPW Erase current IDDE IPPE Unit erase time Total erase time Rewrite count
Note
Conditions When VPP = VPP1 VDD pin VPP pin When VPP = VPP1 VDD pin VPP pin
MIN.
TYP.
MAX. 67 100 67 200
Unit mA mA mA mA s s times V V MHz
tER tERT
0.2
0.2
0.2 20
20 VPP0 VPP1 In normal operation mode In flash memory programming mode 0 7.5 4
20
20 0.2VDD
VPP supply voltage
7.8
8.1 16
Operation frequency
Note Write/erase is regarded as 1 cycle.
38
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
3. PACKAGE DRAWING
176-PIN PLASTIC LQFP (FINE PITCH) (24x24)
A B
132 133 89 88
detail of lead end S P C D T
R Q
176 1 45 44
L U
F G H I
M
J
K S N S M
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 26.00.2 24.00.2 24.00.2 26.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.5 0.17 +0.03 -0.07 0.08 1.4 0.10.05 3 +4 -3 1.50.1 S176GM-50-UEU
Preliminary Data Sheet U14622EJ1V0DS00
39
PD70F3040, 70F3040Y
4. RECOMMENDED SOLDERING CONDITIONS
T.B.D.
40
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
[MEMO]
Preliminary Data Sheet U14622EJ1V0DS00
41
PD70F3040, 70F3040Y
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use these components in an I C 2 system, provided that the system conforms to the I C Standard Specification as defined by Philips.
2
2
2
Related document Reference document
PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Data Sheet (U13953E)
Electrical Characteristics for Microcomputer (IEI-601)
Note
Note This document number is that of the Japanese version. The documents indicated in this publication may include preliminary versions. versions are not marked as such. V850 Family and V850/SV1 are trademarks of NEC Corporation. However, preliminary
42
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Preliminary Data Sheet U14622EJ1V0DS00
43
PD70F3040, 70F3040Y
* The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M5 98. 8

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